Cpu Fan Speed Low Limit Asus Maximus Hero 6

Disclaimer !

These settings and methods
are outside Intel's specifications,
just like some otherwise overclocking method acting.
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Introduction:

In a world increasingly preoccupied with natural resource, the countersign is efficiency. Sol, it's clock time to look at adaptive potential difference and by heart with unusual eyes.

This is not to say that the era of overclocking with "Sync all cores" and "set voltage" is ended, equally it is much easier and faster to do, and brings good results, but it is not "Single Thread" efficient.

It is worth remembering that Intel supplies its processors operative stock in "past core" and "Adaptive Voltage", and instantly goes beyond, and manufactures its processors with operation cores and efficiency cores.

Merely anyway, wherefore would I sell the easiest way to overclock it for a more complicated cardinal? The answer is simple, because we like complicated things. Now a day, with the current processing capableness, it is not necessary to overclock, and even then we do this complicated thing, just for a few spear carrier frames. So we arrange it for fun. The overclock itself can be fun like a game. Later all, isn't information technology discriminating to know that we john go a little over the limit thereupon hardware we bought?

Thanks:

My thanks to Shamino and Asus for every last their support and for inviting ME to link the ROG Maximus Z690 weapons platform test squad.
My sincere thanks to Falkentyne and Cstkl1 for their avail during testing.

Considerations:

The intention of this work is non to provide an overclocking recipe or break records, just to help understand how voltages, frequencies and temperatures work in the octvb configuration.
Asus has great features in its MBs that enable TVB overclocking, but information technology as wel provides a unequalled optimisation tool called "Bradypus tridactylus Overclocking" which works very well.

This guide will cover the basics of Load Lines, By Core Usage, VF Curves, TVB, and OCTVB.

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* * * This procedure fundament be practical to the Z490 / Z590 / Z690 Maximus and Genus Strix MBs with some adjustments. * * *

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INDEX:

• CPU Tycoo Specifications
• By core
• TVB
• OCTVB
• Adaptive Voltage & VF curve
• Taxonomic group Core Accommodative voltage
• Interpolation
• Understanding LLC, AC_LL & DC_LL
• Choosing LLC, AC_LL and DC_LL
• Undestanding the LLC, DC_LL and AC_LL Numbers
• The LLC core
• Setting the Full Consignment frequency
• Defining Lade Lines
• System inauguration
• Adjusting the marginal voltage to full load P-51x / E-40x
• About E-cores
• Defining the By Essence Usage
• System stability examine
• ASUS OCTVB
• Understanding Asus OCTVB
• Notes
• Bios Attachments

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CPU Power Specifications:

By Core:

The "By core" is nothing more than the use of processor cores at different frequencies, depending on the workload.

Below, we find the default oftenness settings for some processors:

*Image credits: SkatterBencher

We volition use the following nomenclature to refer to the frequencies and numbers of cores:

[absolute frequency] X [number of cores gushing concurrently] - [frequence] X [identification number of cores running concurrently] - etc...

Full lode substance all cores are running at the same time on this frequency:

[Full Load] @ P-[absolute frequency] x / E-[frequency] x

Examples:

9900K
50x2 – 48x4 – 47x8
Full loading @ 47x

10900K
53x2 – 51x4 – 50x6 – 49x10
Full phase of the moon load @ 49x

11900K
53x2 – 52x4 – 51x6 – 49x8
Full warhead @ 49x

12900K:
P: 52x1 – 51x2 – 50x4 – 49x8
E: 39x4 – 37x8
Overloaded load @ P-49x/E-37x

* Data from an 12900k CPU read by Asus OCTool.

TVB:

[/B]

The emblematic CPU has a standard time speed and a turbo boost speed. However, CPUs with Hot Velocity Boost have two additional Boost speeds. As wel known as Intel TVB, the feature is available on 10th, 11th, 12th generation desktop chips.

TVB is a technology that takes advantage of the processor's thermal "opportunity" to increase its working frequency.
Thermal Velocity Cost increase allows these CPUs to achieve even higher encouragement speeds than their typical turbo boost.

This means that in addition to its standard clock hurrying and Boost of whol cores, an Intel CPU can have four additional speeds.

Turbo Boost 2.0 is a respective-core Boost available if the CPU is continual to your power, current, and temperature specifications.
The speed of turbo boost max 3.0 applies to two favorite cores. It is only possible if the Processor is running below its power, current, and temperature specifications.
Thermal Speed Boost takes the fastest of the two loved CPU cores at a high speed than it gets with turbo hike up easy lay 3.0.
This is only possible if the Central processor is running below 70 degrees Celsius and if the CPU is running to a lower place its power, current and temperature specifications.

The thermal speeding increase of all cores refers to the reachable speed if all cores are active and the CPU is operational nether its various temperature limit (70 degrees Celsius).

OCTVB:

The TVB overclock consists of changing boost patterns to achieve higher frequencies than standard when there is a thermal opportunity.

E.g. You can change the Boost of the 12900k to body of work this way.

Before +2Boost Profile:

P: 56x2 – 55x3 – 53x5 – 51x8
E: 42x4 – 41x6 – 40x8
Brimfull load @ P-51x/E-40x

After +2Boost Profile:

P: 58x2 – 57x3 – 55x5 – 53x8
E: 42x4 – 41x6 – 40x8
Full load @ P-51x/E-40x

Note:
The Boost Profile will never be applied to the E-Cores.
The Full Encumbrance frequency will be the raw "By core" overladen laod due to temperature.

* Asus OCTool - Intel Monitor

Applying the Rise Profile, various rules are practical to the combination of frequency x cores so that the CPU takes advantage of the low temperature to accomplish high alfilaria.

* Asus OCTool -CPU OCTVB

What we simply do is set upwards a new TVB: if the workload is underslung, the frequency volition represent high, and when the workload is high, the frequence will be glower.

Changing TVB, or rather overclocking TVB, we come to Asus OCTVB.

Warning:
For OCTVB to work, you need to enable C-States !

Adaptive Potential difference & VF curve:

Unlike the "fixed Voltage", the "Adaptive Electric potential" and "VF curve" behaveso as to monitor the absolute frequency.
High frequencies require higher voltages, lower frequencies, lower voltages.

Every processor comes standard with an internal VF bender that we can't change.
Asus MBs allow U.S.A to supply an offset (positive or negative) to these points of the original curve.
So, we can aver that Asus allows us to change the "voltage x frequency" Central processor curve.

These values can be found in the BIOS on this page:

NOTE:
The default on setting for VF #11 is 5300MHz. In the image in a higher place, "By core usance" changed this frequency to 55x
And +2Boost Profile changed information technology again, to 57x.

Asus allows U.S.A to change the voltages of every points through with the setoff and allows us to transfer the oftenness only of the last orient through and through the "By Core usage " place setting.
This VF cut shows the electromotive force that the CPU will use for a specific frequency.
When CPU is spouting 4800MHz, the VID used will be the VF#6, as well VF#5 is the VID of 4200MHz.
So the CPU is changing the voltage all the prison term, and these voltages can be modified by some factores equivalent LLC and AC_LL

When we assign a oftenness to a number of cores using "By Core Usage", the highest frequency will adopt the last point happening the VF twist.

Note:
When we apply a Promote, this Advance will be applied to the last point of the VF curvature.

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Watch out here!

Note that the maximum frequency set in "By Core Use" is 55x.
So why is the last melodic phras of the VF curve (VF #11) 57x?

The explanation is easy:
The "Per nucleus exercis" is the raw frequency, without any OCTVB boost.
When boost is applied, you will see the higher frequency boosted int the VF curves.
(To see the boosted frequency in the VF trend you need to "relieve and exit" after selecting the Boost visibility and entre BIOS once more)

If you neediness to point of accumulation some core frequency, you should limit the raw "By core usage" frequency.
So, in the example below, with +2Boost profile, core 0 and core 1 are restricted to 57x (not 55x) and cores 2 and 3 to 56x (non 54x)
If you are using +1Boost profile, core 0 and core 1 volition be limited to 56x (not 55x) and cores 2 and 3 to 55x (not 54x)

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Therefore, the minimum "By core usage" frequency (51x) will be the full load frequency and the highest will be the highest plus the hand-picked booster.
Therein character, the + 2Boost profile was applied.

Sol, for our TBV overclock, the important points will e'er be the last two in the VF curve.
The points VF#7 and VF#8 for the 10900K and 11900K and the POINTS VF#7 and VF#11 for the 12900K.
Points VF#8,9 and 10 in the 12900K will not beryllium used and must remain in Motorcar.

About ADL VF curve

1-7 are unique points,
11 is OC point (user can change this ratio). This is the only ratio user can change connected this curve.
8-10 are copies of 7
7 is the unlikely unusual point

The rule appears to be when ratios are the aforesaid, point 7 must be >= point 8 otherwise it will MCA
Acode does non like when point 7 electromotive force offset is less than point 8
If you want to program 7 negative, you essential program point 8 disadvantageous first
If you want to program point 8 positive, you must program point 7 positive first
If you don't follow this rule then Acode throws MCA

If programming a negative runner to bespeak 7, good way is to showtime with point 10 and program it negative, then go to 9,8, and 7 programing them all the same disadvantageous measure
If programming a positive offset to only point 8, unsurpassed way is to start with 7 and so go to 8,9, and 10 programming them all to the aforementioned positive value

Specific Core Adaptive voltage:

The Specific Core Reconciling Voltage is a resource that allows you to set the adaptive voltage individually for each core.
The goal is to set more voltage to the worst cores and less voltage to the best cores.

The Specific Core Adaptive voltage is a step on the far side, to be old later on you are stable using the world adaptive voltage.

Let's allege we are running the max frequency of 5700MHz and the system is stable with a global adaptational voltage of 1460mv.
So, at this point, we do it that 1460mv is enough for the worst cores run 57x.
With this logic, if 1460mv is enough for the worst cores, believably the top cores bottom run this frequency with less than 1460mv.

But how fewer? That is what we are going to have a go at it.

The first step is to move into BIOS at the IA Optimization varlet and note of the P-cores VIDs from Core0 to Core7.

This information will record us the worst core VID. In the instance above, kernel 4.

Now we screw this nub will need 1460mv to run 57x. Whol the others cores will be able to run 57x with less voltage.
Today let's get hold the voltages we will need to run 57x for the others cores.

The math is simple:

Specific Core Adaptive Voltage = (Global_Adaptive) – [(Worst_Core_VID) – (Core_number_VID + offset_for_this_core)]

So, for the world adaptive of 1460mv (the one that our system is stable) and the specific core VID shown in the bios paginate to a higher place, we will have the following values:

* We will not utilisation any particular nub offshoot in real time.

Global_Adaptive=1460
Worst_Core_VID=1329

Core0 = (1460) – [(1329) - (1299)] = 1430mv
Core1 = (1460) – [(1329) - (1299)] = 1430mv
Core2 = (1460) – [(1329) - (1304)] = 1435mv
Core3 = (1460) – [(1329) - (1304)] = 1435mv
Core4 = (1460) – [(1329) - (1329)] = 1460mv
Core5 = (1460) – [(1329) - (1289)] = 1420mv
Core6 = (1460) – [(1329) - (1319)] = 1450mv
Core7 = (1460) – [(1329) - (1284)] = 1415mv

A you ass see at the image below.

So, using these Specific Marrow Adjustive Voltages you will run as stable American Samoa before when you were using the spherical Adaptive voltage, with the vantage of reduction the Vcore when spoilt cores are sleeping.

A tip about " Specific Core Adaptive voltage offset".

You tin can use the Specific Core Adaptive voltage outgrowth to "anneal" the cores voltages American Samoa you hindquarters visualize below.
But I assume't remember it is the best scheme.

You can download my Excel voltage tool to help you with this maths.

Interpolation:

In mathematics, linear interpolation is a method acting of curve fitting using linear polynomials to reconstruct new information points inside the range of a discrete set of known data points.

We can use interpolation to find a electromotive force between two VF points, operating room 'tween the finis VF point and the adaptive voltage.

So let take as an example the following VF sheer with an OC frequency of 5700MHz:

The 5100MHz VID is in some place between VF#6 (1184) and VF#7 (1299)

To find the estimated 5100MHz VID we will apply the following formula:

5100_VID = (VF#7_VID - VF#6_VID ) / (VF#7_freq - VF#6_freq) * (5100 - VF#6_freq) + VF#6_VID
5100_VID = (1299 - 1184) / (5300 - 4800) * (5100 - 4800) + 1184
5100_VID = (115) / (500) * (300) + 1184
5100_VID = 1253mv

So the estimated VID for 5100MHz will be 1253mv

If you apply a negative offset of 50mv to VF#6 you must use the new VF#6_VID value to find the recently 5100_VID
So, in this case, the new 5100_VID is 1245mv.
You rear increase or lessen the 5100_VID by ever-changing the VF#6 offset surgery the VF#7 offset.

Care here because if you decide to change VF#7 this will have an upshot on the interpolation of VF#7 to the adaptive emf.

The voltage that wish equal applied at the maximum OC frequency wish be the adaptive voltage operating theatre VF #11 (whichever is high).

In this example, the Adaptive is higher than VF#11
Adaptive = 1458
VF#11 + offset = 1445

Then now let's find the estimated 5500_VID with a 20mv positive offset practical to VF#7:
VF#7 = 1299
VF#7+offshoot = 1299+20 = 1319mv

5500_VID = (Adaptive- VF#7_VID+kickoff) / (OC_Freq - VF#7_freq) * (5500 - VF#7_freq) + VF#7_VID+counterbalance
5500_VID = (1458 - 1319) / (5700 - 5300) * (5500 - 5300) + 1319
5500_VID = 1389mv

The interpolation is a linear curve as you can see below.

You can download my interpolation tool here.

Understanding LLC, AC_LL & DC_LL:

Let's first understand load lines:

For this, didactically, we will commutation the electric current for a flow of water.

Our goal is to adjust the circuit so that the tanks remain at the aforementioned levels at all multiplication, regardless of LOAD.

The resistance to the enactment of water in the "Load Pedigree" piping is physical and intrinsic to its building.
(This is the corporal wire from the VRM to the CPU).

As the LOAD varies every the time, the CPU tank level tends to undergo higher or lower than the VRM tank in an uncontrolled way.

So allow's require control !

For that we have 2 pumps: the LLC pump and the AC_LL pump.

The first affair to do is to choose an LLC pump that will compensate for losses in the Plimsoll line pipe.
(This is the VRM impedance characteristic, which determines the voltage drop As up-to-date flows).
Ideally, the pump should live neither too strong nor too weak.

We have 8 LLC pumps to choose from.
Pumps #7 and #8 are same forceful and are not viable for daily use. Thus we have six pumps left.
IT seems to me a good idea to select an medium pump, #3 for example, but we can choose any one of these 6 pumps, atomic number 3 lengthy A we fix adjustments in the negative feedback circuit.

All this control will embody done by the CPU, so we mustiness inform which pump we choose through the DC_LL parameter. This way, the apprais of DC_LL (milliohms) essential touch the value of LLC (milliohms) chosen indeed that the C.P.U. does all the calculations correctly.

The next pump to take is AC_LL.
(This is the load variation compensation component).

This parametric quantity makes the CPU, upon perceiving an increment in the water flow to the LOAD, to increase the VID value sent to the VRM, systematic to anticipate the losses that this flow increase could cause. Therefore, the VRM uses the LLC and AC_LL pumps to fulfill the CPU VID request.

Indeed if we have a stronger LLC pump, we can use a weaker AC_LL pump and frailty versa.

Or s combinations are not recommended, for example: 2 weak pumps operating theatre deuce strong pumps.

All this crippled bum be cooked according to the desired goals.

Comparison with frozen voltage:

When we decide to use "voltage override" we switch off all this controls represented before.
The selected LLC pump and the VID manually set will eat the flush of the Central processor tank without a control condition.
In this cause, when the hang to the load rises, the level of the C.P.U. tank goes down... And when the flow to the onus decreases, the level of the CPU tank goes up...
So, bye bye level control.... 😂

You will need to pass over totally the time with much voltage than you need, for that specific frequency, just waiting for when the heavy loading comes.

If you think you hind end do a better job than the Central processor algorithm, habit fixed voltage, Don River't worry about AC_LL and DC_LL. Set an LLC #5, 6 or 7...
But I think it's a better idea to use this extra voltage to reach high frequencies...

Choosing LLC, AC_LL and DC_LL:

The best step in preparation overclocking is to set the full-of-the-moon encumbrance relative frequency.

But for everything to put to work well, and as predicted, we essential first set up the LLC, AC_LL and DC_LL.

If the selected High Load frequency has a unique VF point for this absolute frequency, we will be more free to choose LLC, DC_LL and AC_LL.
Other than, if the Whole Loading frequency does non have a specific VF spot, we will have to choose the best Charge Line set up that allows us, through with interpolation of the points, to set the voltage referring to the frequency chosen for Untasted Load.

The basic rule of adaptive voltage and TVB overclock (OCTVB) is to work with vdroop to your advantage.
This mode, using a less aggressive LLCs will give you greater margin for high frequencies.

In a simplified way, load personal line of credit should mold overclocking As follows:
Broken heaps, low Vdroop, high voltages, high frequencies.
High loads, high Vdroop, low voltages, low frequencies.

You can configure the TVB overclock using any LLC, IT all depends connected your processor and what you want to do with it.

This Is the Board Maximus Z-690 Extreme LLC Impedance:

LLC1: 1.75 milliohms
LLC2: 1.46 milliohms
LLC3: 1.1 milliohms
LLC4: 0.98 milliohms
LLC5: 0.73 milliohms
LLC6: 0.49 milliohms
LLC7: 0.24 milliohms
LLC8: 0.01 milliohms (flat).

The impedance values of the DC_LL shall be used accordant to the LLC chosen, thusly that the Central processor performs its home potential difference and power calculations accurately.

Impedance stake:
DC_LL=LLC: The CPU performs correct VID and mogul calculations;
DC_LL<LLC: The Central processor performs higher than real VID and powerfulness calculations;
DC_LL>LLC: The CPU performs lower than real VID and power calculations.

So, rule is: E'er TUNE The DC_LL according to the LLC Chosen.

Below are whatsoever configuration suggestions for the 12900K:

LLC#1
DC_LL = 1.75
AC_LL = 0.60

LLC#2
DC_LL = 1.46
AC_LL = 0.46

LLC#3
DC_LL 1.1
AC_LL 0.25

LLC#4
DC_LL 0.98
AC_LL 0.20

Undestanding the LLC, DC_LL and AC_LL numbers:

LLC controls the output impedance of our VRM, and MB vendors allow us to change and control this resistivity.

DC_LL is the parameter that informs the Central processing unit the VRM impedance.
If you adjudicate to use LLC #1, the electric resistance is 1.75mohm, then you need to inform the CPU of this impedance using the DC_LL parameter.
If you use LLC #4 then the DC_LL should be 0.98.

To find the LLC impedance, you need to prove one by one LLC and change the DC_LL until the VRM power matches the CPU power and the VID matches the Vcore. Once they match, you found LLC impedance.

AC_LL is a parametric quantity that compensates for voltage expiration attributable your load line impedance, and you need to guess and test a different number for each LLC.

If you use a high impedance LLC you will need a high AC_LL, on the other hand if you usage a low impedance LLC you will need a low AC_LL
Note that along Asus MB, LLC # high means lowly impedance. And LLC # low means high electrical resistance.

So never use a depressed impedance LLC with a in flood AC_LL... This will result in a very high electromotive force....
That's why I recommend an IA VR voltage limit of 1500mv....
So if you institutionalize an error, the voltage will have a limit of 1.50v.

Simplifying the formulas:

You have the VF curved shape VID... Lashkar-e-Toiba's call it raw-vid.
That VID you see in hw-info, allow's call information technology VID
You have the LLC electric resistance, let's telephone call it LLC#
You have the DC_LL electrical resistance parameter, permit's call it DC_LL
You hold AC_LL ohmic resistance recompense, let's call it AC_LL.
You have the C.P.U. actual, let's call it Amp.
You have the offsets and temperature components that we'ray not going to use to constitute things easier right now.
You have the Vcore, and let's call it Vcore.

So....

VID = raw-vid + (AC_LL * Amp) - (DC_LL * Amp)

Vcore = raw-vid + (AC_LL * Amp) - (LLC# * Amp)

This is how I found the LLC resistance.
If DC_LL = LLC than VID=Vcore at full moon load.

The Intel recommendation is to use AC_LL = DC_LL and LLC#3 (for asus Megabyte)
So the intel recommendation is:

LLC = 1.1 mhom
AC_LL = 1.1mhom
DC_LL = 1.1mhom

It's a very buttoned-up mise en scene that will put to work with some poor MB.
Using AC_LL = LLC #, the lost voltage caused by VRM impedance leave be compensated by AC_LL.

Merely we want to UNDERVOLT the Central processor, true?

So, we will use AC_LL < DC_LL

But how to find the correct numbers?
Testing the combinations.
For each one CPU will respond depending on the Si lottery.
I've made suggestions here, soh you'll pauperization to understand all of this and make some department of corrections.

The LLC outcome:

Many like to tinker with their motherboard load-line settings to achieve better overclocking results. Simply how does this setting really work and how does the voltage output change with it? Mark to a lower place to find out.

What is Load-Line?
The load-line scene, ordinarily in mΩ (milliohms), determines how much the output voltage decreases when loaded. This is derived from Ohm's Jurisprudence U = R*I. The drop in output voltage is calculated atomic number 3 load-line * Iout (output present-day). For example a laden-pedigree of 1 mΩ and output actual of 100 A, dU = 0.001 Ω * 100 A = 0.100 V. At 1.300 V set-point turnout potential, when intoxicated with 100 A the output signal would really be 1.300 – 0.100 = 1.200 V. The primary reason for using a freight-line in modern systems is to reduce voltage spikes (overshoot) when going from high to Low output current and achieve a more predictable behavior.

Cargo-Line of credit Levels OR like-minded are profiles created by motherboard manufacturers to obfuscate and "simplify" other load-line values for users. Another reason for these profiles is because additional VRM (Voltage Regulator Mental faculty) settings may need to adjusted along with the load-line value to keep it operating inside spec.
The captures at a lower place show the production voltage short-lived behavior when loaded with about 70 A for ~150 μs. The LLC1 capture illustrates ideal load-line demeanour.
As the load-line treasure decreases (higher point), the line flattens and the below/go-around spikes at start and cultivation become more pronounced.
The last-place voltage point at the beginning of the load transient does not improve much. In this case, victimisation a Loading-Line Level off of above 3 seems questionable.
The burden voltage would increase pregnant high power use of goods and services, but the worst slip lowest voltage would last out the same.

Credits: ElmorLabs

Place setting the Full Load frequency:

P-51x/E-40x is a Full Load frequency that almost all 12900k processors can backup, flush with an AIO typewrite cooling solution, so we'll follow with this example.
(If your CPU does non support this configuration due to high temperatures, you can try the P-50x / E-39x.)

Now we must determine out what the minimum voltage for the inundated load frequency, in a way of life to optimize the working temperature of the Processor and the dissipated power.

To find the minimum voltage for Full Load we deman to sync altogether carrying out cores at 51x and all efficiency cores at 40x.

The traditional way is to set load lines (e.g. LLC#4, AC_LL=0.20, DC_LL= 0.98), choice "Sync All P-Cores" to 51x and "Sync all E-Cores" to 40x, set a value to "Fixed Potential difference" and then find the minimum Vcore voltage that maintains system stability.

This is a good way to bugger off started, as we'll already know the minimum Vcore in gain to maintain stableness at cram full load P-51x/E-40x.

But let's bash something contrasting to get us started using "By Core".
Instead of selecting "Sync All Cores", let's select "By core usage" and set all P-cores to 51x and all E-cores to 40x

This direction totally cores will be synchronised and overflowing load will be P-51X/E-40x.

Defining Consignment Lines:

At once we must choose which LLC we will function for our OCTVB.

(If you used LLC#4, AC_LL=0.20, DC_LL= 0.98 to find the minimum voltage for Full Load by synchronizing the cores, now it's clock time to go back to LLC#1 to use Vdroop to our advantage for stinky frequencies.)

Let's start past examination LLC#1:

Now let's tune AC_LL and DC_LL to LLC#1
AC_LL= 0.60
DC_LL= 1.75

And set the "IA VR Potential Limit" to 1500mv.
This configuration will avoid whatever voltage higher than 1.50V with the penalty of some high frequencies.
*** The Value of 1500mv is a pesonal prize. You give the axe try 1550, 1600 or 1700.

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IA VR Voltage Limit

Asus included in the BIOS of its Z-690 MBs the control "IA VR Potential dro Limit".
This control limits the VCore voltage to the selected value, preventing the CPU from reaching frequencies that require higher voltages than the chosen incomparable.
In practice this control limits the maximum CPU absolute frequency based on the voltage limit of the established VCore.

The nonpayment note value (AUTO) is 2500mv, that is, away default there is no relative frequency limitation due to Vcore voltage.
This control will be very effectual for constraining the highest frequencies while maintaining system stability.
Arsenic a mesmerism, the initial value of 1500mv is quite an reasonable.

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System startup:

Boot the system with the following settings:

LLC=#1
AC_LL=0.60
DC_LL=1.75

C-State = Enable
Electric potential Optimization = Enable
IA VR voltage Limit=1500 (or the trammel you think is good for you)

Aside inwardness = P-51x8 / E-40x8
Adaptive voltage (Machine)

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It's clip to test system stableness in Afloat Load.

Run the CB-R23 and gibe the stability of the system.

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If the system is not steady change to the LLC#2 settings:

LLC=#2
AC_LL=0.46
DC_LL=1.46

C-Country = Enable
Voltage Optimisation = Enable
Iowa VR voltage Limit=1500 (or the limit you think is good for you)

Past core = P-51x8 / E-40x8
Adaptive voltage (AUTO)

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Keep going increasing the settings of the Load Line set until you attain constancy by running the CB-R23.

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Note: It is rattling likely that using the LLC#1 settings the system leave be stable, with just voltages and temperatures.

If the system is stable running game CB-R23, write down the full load values:

Core_VIDs =
Core_Clock_P =
Core_Clock_E =
Core_Temp =
IA_Core_Power =
Vcore =
CPU_Core_Current =
VRM_Vcore_Current =
VRM_Vcore_Power =

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If the Load Lines configuration was done aright you will see that vrm power (VRM Vcore Power) and CPU power (IA Inwardness Power) will have same close values at Well-lined Encumbrance. The synoptic will happen with VID and VCore.

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Adjusting the minimum potential to full load P-51x / E-40x

Now it's time to lower Vcore to the lowest possible level patc maintaining system constancy, even as we set when victimization "sync wholly cores" and "fixed voltage".

To do this you can exercise Asus OCTool, Asus's exclusive puppet for dynamic BIOS parameters "on-the-fly".

*To use this tool, disable "Windows Memory Integrity" and/or "Intel VMX" in BIOS.

For those who do non induce an ASUS Megabyte the solution is to each change reboot the system to make changes at once to the BIOS.

Offset changes to VF points made with OCTool are not everlasting, and on an future system restart the BIOS settings volition be reapplied.
The offset values circumscribed with OCTool should hence be applied again to apiece reboot.

Note: Around OCTool functions can be appraising, so if you wear't know what it's for, don't hatful with it. 😊

With OCTool you hindquarters do the entire VCore adjustment procedure for full load with few system reboots.
Once the value of the offsets that generate the in demand VCore has been found, these values should be practical directly to the offsets of the BIOS VF curve.

Disregardless of which method you use, the process will be the homophonic: use the points of the VF curve to reduce the VID of the full load frequency.

If the VF set back has a VF point for the chosen full payload frequency, simply reduce the VID of this point until it is no longer possible to run the CB-r23 and/or the system becomes unstable. In this case we should use of goods and services a VID 5mv or 10mv above the stability limit.

If there is no more unique point for brimming load frequency (as in the case of the 51x frequency of 12900K), you will need to take down the voltage of the table points in front and/or later on the selected instinct load frequency.

In our example of the well-lined load 12900K (P51x), the near command points are VF#6 (4800MHz) and VF#7 (5300MHz). Although the P51x is closer to the VF#7 (53x), a negative offset at this point is not a good option to keep down the full shipment voltage of the 51x absolute frequency, as the voltage step-dow of this point will influence the interpolation voltage of frequencies greater than 5300MHz. Thus, we must employ the VF#6 to reduce the full warhead voltage of 5100MHz.

Let's start by fashioning a reduction of 10mv at 10mv at the VF#6 point until it reaches a point where the CB-r23 becomes unstable. After finding the point of instability, honorable gain the offset of VF#6 by 10mv, test again, and if the arrangement is stable, we can drop a line this VF#6 offset directly into the BIOS.

Since the relative frequency and afloat load voltage are already set, it is time to hardened the other nerve impulse frequencies.

About E-cores

In that location is none VF curve for the E-cores. So how can I know the minimum potential dro for for each one e-pith frequency?
First, you need to sync all e-cores to 40x.
In Windows, select the power programme "Power Saver" and streamlet r23. Indite downwardly the VID of the e-cores.
If you want to know the potential for 41x, 42x, etc, synchronize each e-cores and repeat the trial run.

The entire load VID of the P-cores must comprise ample for the E-cores, otherwise the system will crash.

Shaping the By Core Usage:

You can define multiple core groups to specify to them a specific frequency, OR fair define the absolute frequency groups and Lashkar-e-Taiba the CPU itself specify which cores leave operate on inside a group and at what time.

Examples of configurations for performance cores:

P: 58x1 - 57x2 - 56x3 - 55x4 - 54x5 - 53x6 - 52x7 - 51x8 (Eight frequency groups)

P: 58x1 - 57x3 - 55x5 - 53x7 - 51x8 (Five frequency groups)

P: 57x3 - 55x5 - 53x6 - 51x8 (four frequency groups)

P: 55x3 - 53x5 - 51x8 (Three frequency groups)

American Samoa we sic the full load frequency to 5100MHz, any configuration adopted must respect the value of 51x for the maximum number of cores (51x8).
Whatever the configuration chosen, total of groups or maximum frequency, so that the full loading on P51x is respected we moldiness assign the 51x to the 8 cores.

The same conception applies to efficiency cores.

We will adopt the favourable conformation as a protrusive point in time:

LLC=#1
AC_LL=0.60
DC_LL=1.75
(or the Plimsoll mark set of your select to accomplish rich lading Vcore for P-51x/E-40x)

C-Submit = Enable
Emf Optimisation = Enable
Iowa VR voltage Limit=1500mv (Oregon the limit you think is healthy)

VF#6 = Negative offset (the one you have already saved for Full Load)
VF#7 = positive offset 40mv (this is a suggestion that will help you tend high OCTVB frequencies)
VF#11 = undeniable outgrowth (1.46 - VID of point #11) ***
Adaptive electric potential = 1.46v

By core employment
P: 55x3 – 53x5 – 51x8
E: 42x2 – 41x4 – 40x8

*** Notice: Retention the value of the sum of (VID_VF#11+offset) penny-pinching to the adaptive voltage value helps in system stability.

When you feel comfortable you can use asus OCTool to set values "connected-the fly".

System constancy test.

We know that for afloat load frequencies the system is stabilised, it remains to be legendary if it is stable for light mountain.
The primo stableness test for high frequencies is the utilization of the computer for basic tasks like surfboarding the internet, YouTube, etc...

The Aida memory latency try is a good way to check the rough-and-ready time of the core0.
The CB-r23 ST is also a good agency to assert that the organisation is responding at frequencies greater than P-51x in ST.
The RealBench is nifty to essa the "groundless to full payload to idle" stability.

ASUS OCTVB:

Once the system is unfluctuating it is clock to enable Asus TVB profile.

By maintaining the previous settings, simply enable "TVB overclocking" = +1Boost Visibility.

*TVB Boost is applied to P-cores simply.

In this manner, we wish have the system operating as follows:

Frequencies:
P: 56x3 – 54x5 – 52x8
E: 42x2 – 41x4 – 40x8
Full Load-51x/E-40x

Note that when the 8 P-cores are loaded the frequency is now 52x, however several temperature rules are applied so that fully load the CPU keeps the 8 P-cores at 51x due to temperature.

Whatsoever organisation instability from immediately connected will flow from to the high frequencies, never collectible to the full load frequency (forward you have right set the full load potential antecedently)

If you encounter instability at sick slews, the following actions rear help you return to constancy:

Rise Adaptive Electromotive force;
Surface VF#7;
Rise VF#11;
Rise IA VR Voltage Limit;
Lower max "by core" freq and/or Boost.

If you bump instability at heavy gobs, the following actions can help you return to stability:

Rise AC_LL;
Rise VF#6;
Change the LLC set.

If you have temperature problems, sample to lower the full load up frequency.
You can try full load at P-50x / E-49x, or any other combination.
Call up to find minimum Vcore for the newborn frequence selected.

If your system is unchanging, it's time to go to the Asus "+2Boost visibility" and run whether your system will be able to run in the following configuration:

P: 57x3 – 55x5 – 53x8
E: 42x2 – 41x4 – 40x8
Ladened Load: P-51x/E-40x

After all done and stable, run somes terrace tests…
The Tonne results must atomic number 4 appropriate P-51x / E-40x
The ST results will be temp dependent.
The Aida memory latency test is good check the effective ST time .

Understanding ASUS OCTVB:

I'll try to stimulate OCTVB easy...
Let's purpose my actual manual OCTVB settings as an example:

Early line is for exclusively 1 fighting P-core.
So this line will be used when only 1 core (anyone) is active, and the others are parked or not loaded.
In this condition, If Marrow temp is < 60 this core bequeath run 57x.
If temp is 60 to 69 this core will run 56x.
If temporary worker is >= 70 this core will run 55x

The second line is for when 2 cores (anyone) are active and the others are sleeping or not loaded.
If temporary worker < 56 these 2 cores will run 57x.
If temp is 56 to 65 these 2 cores will run 56x
If temporary is >= 66 these 2 core testament run 55x

The tierce line is for when 3 cores (anyone) are active and the others are sleeping operating theater non loaded.
If temp < 52 these 3 cores will foot race 57x.
If temp is 52 to 61 these 3 cores testament unravel 56x
If temporary is >= 62 these 3 core will run 55x

The fourth line is for when 4 cores (anyone) are active and the others are sleeping or not loaded.
If temp < 66 these 4 cores will extend to 55x.
If temporary is 66 to 75 these 4 cores wish run 54x
If temp is >= 76 these 4 core will run 53x

So let's go to the last line....

The go line is for when all cores are active and loaded.
If temporary < 72 these 8 cores volition run 53x.
If temp is 72 to 81 these 8 cores will run 52x
If temp is >= 82 these 4 core will run off 51x

Once understood lets try some tricks:

You can employ "8 Active Core tempB" = 100C to change the full load logic.

This way your full load will follow 52x, because when 8 cores are active and loaded, and temp hit 72 the freq. will drop from 53x to 52x... and the next temporary step is the TJmax.

Another trick:

You crapper chage the BinA (or BinB) to effect 2 drops:

Thusly when 8 Active cores are loaded and temp hits 72C, freq. will glucinium 51x, and when they hit 82C, freq. will be 50x.

TempA is joined to BinA and TempB is Linked to BinB

You can change BinA and BinB changing the frequency more than 1 step in any situation.

Adding few "º C" to the table:

This table at a lower place is an Asus +2Boost profile automatically calculated by the Asus algo for the following "away core" configuration:
58x2 - 57x3 - 55x5 - 53x8.

You can edit all the temps adding a few degrees..

+15C to the 53x8 (6,7,8 active cores)
+ 5C to the 55x5 (4 and 5 proactive cores)
And keep 57x3 and 58x2 untouched.

And you can taste whatever kinda combination that you derriere flush... LOLOLOL

I use to mental test with the Asus OCTool and when I find some nice setting I publish to the BIOS.

Under you can see a literal example:

This is the Asus +2 Boost Visibility

Applied +5ºC to the whole table:

Applied +10ºC to the entire table:

Below we changed the gas-filled load frequency from 51x to 52x place setting 100C to the "8 Brisk Core" TempB

Notes:

The use of LLC#1 was purely a grammatical category alternative. The procedure is sensible for any LLC# that you find most convenient.

The 1500mv "Hawkeye State VR Emf limit" limits the Vcore voltage and the maximal frequency of the OCTVB, this value was also a personal choice.

The default LLC is the #3. If you want to keep your hardware overclocked as close to spec as possible, use the LLC#3 situated:

LLC#3
DC_LL 1.1
AC_LL 0.25 (if you take up a really angelical CPU, you can try decrescendo AC_LL from 0.25 to 0.20. If your CPU is not so echt, try 0.30 or 0.35)

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MY BIOS Background
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Cpu Fan Speed Low Limit Asus Maximus Hero 6

Source: https://www.overclock.net/threads/asus-maximus-z690-extreme-i9-12900k-guide-load-lines-vf-curves-adaptive-voltage-by-core-octvb.1794957/